DocumentCode :
2567394
Title :
PAFESD: Process algebras for electronic system designs
Author :
Man, K.L.
Author_Institution :
Univ. Coll. Cork, Cork
fYear :
2007
fDate :
22-25 Oct. 2007
Firstpage :
110
Lastpage :
113
Abstract :
In this paper, we review a number of process algebra based formalisms that can be used for the formal specification of electronic system designs. It should be of interest to architects, engineers and researchers from the electronic design community. This paper also covers various formal techniques (process algebra based) for analysis of electronic system designs. Furthermore, we devote some space in this paper to an brief introduction of two process algebraic theories/frameworks SystemCFL and PAFSV that can be regarded as the formal languages of SystemC and SystemVerilog respectively.
Keywords :
formal languages; formal specification; hardware description languages; process algebra; PAFESD; PAFSV; SystemCFL; SystemVerilog; electronic design community; electronic system design; formal language; formal specification; process algebra; Algebra; Automatic control; Computer science; Context modeling; Control systems; Design engineering; Formal languages; Formal specifications; Hardware design languages; System-level design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
Type :
conf
DOI :
10.1109/ICASIC.2007.4415579
Filename :
4415579
Link To Document :
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