On Extended Graph-Based Rewiring Technique

The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods being able to further improve some already excellent results on many EDA problems, starting from logic minimization, partitioning, FPGA technology mappings and final routings. Previous studies show that GBAW, a graph-based rewiring engine, is able to outperform ATPG-based rewiring tools with 50-time faster runtime while being able to cover nearly half target wires in the circuit. This paper presents several new improving extensions on GBAW, including coverage of arbitrary gate sizes, to improve its rewiring power. Experimental results based on MCNC benchmark circuits show that, compared to previous GBAW, this new version is able to cover 12% more target wires and provide 1.5 times more alternative wires while runs over 100 times faster than its ATPG-based counterpart. For some problems only requiring a good-enough and very quick solution, this new rewiring technique may serve as a useful alternative.