Author :
Brox, M. ; Fibranz, H. ; Kuzmenka, M. ; Lu, F. ; Mann, S. ; Markert, M. ; Mbller, U. ; Plan, M. ; Schiller, K. ; Schmölz, P. ; Schrögmeier, P. ; Tauber, Arne ; Weber, B. ; Mayer, P. ; Spirkl, W. ; Steffens, H. ; Weller, J.
Abstract :
A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping elements eliminate the level degradation of the receivers caused by an oscillation of the on-chip ground. A technique for cancelling line-to-line coupling noise is also described
Keywords :
DRAM chips; integrated circuit design; integrated circuit noise; system-on-chip; 2 Gbit/s; 512 Mbit; DRAM; averaging pad driver design; level degradation; noise reduction; on-chip ground; resistive damping elements; simultaneous switching noise; Acceleration; Bandwidth; Graphics; Jitter; MOS devices; Parasitic capacitance; Propagation delay; Random access memory; Resonance; Voltage;
