• DocumentCode
    2567465
  • Title

    A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

  • Author

    Dong Uk Lee ; Hyun Woo Lee ; Ki Chang Kwean ; Young Kyoung Choi ; Hyong Uk Moon ; Seung Wook Kwack ; Shin Deok Kang ; Kwan Weon Kim ; Yong Ju Kim ; Young Jung Choi ; Moran, P. ; Jin Hong Ahn ; Joong Sik Kih

  • Author_Institution
    Hynix Semicond., Ichon
  • fYear
    2006
  • fDate
    6-9 Feb. 2006
  • Firstpage
    547
  • Lastpage
    556
  • Abstract
    A series pipelined CAS latency control with voltage-controlled delay line that extends maximum data rate to 2.5Gb/s/pin at 1.7V, is presented. Other schemes applied in the DLL are dual loop control that increases power noise immunity and LPDCC that achieves low power consumption. All these schemes are implemented in a 8M times 32 device using a 0.10 mum DRAM process
  • Keywords
    DRAM chips; delay lines; delay lock loops; low-power electronics; voltage control; 0.10 micron; 1.7 V; 2.4 Gbit/s; CAS latency control; GDDR3 SDRAM; LPDCC; dual loop digital DLL; power noise immunity; series pipeline; voltage controlled delay line; Clocks; Content addressable storage; Delay; Digital control; Frequency; Graphics; Inverters; Jitter; Pipelines; SDRAM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    1-4244-0079-1
  • Type

    conf

  • DOI
    10.1109/ISSCC.2006.1696091
  • Filename
    1696091
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2567465