Title :
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8:4 Multiplexed Data-Transfer Scheme
Author :
Fujisawa, Hiroyuki ; Kubouchi, S. ; Kuroki, Kenji ; Riho, Yoshiro ; Noda, H. ; Fujii, Ichiro ; Ito, Takao ; Tanaka, Hiroya ; Nakamura, Mitsutoshi
Author_Institution :
ELPIDA Memory, Sagamihara
Abstract :
The column access time of a 512Mb DDR3 SDRAM implemented in a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through an 8:4 multiplexed data-transfer scheme that enables the use of shielded I/O lines. A dual-clock additive latency counter enables a 30% reduction in cycle time from 1.7 to 1.2ns. By combining these with a multiple on-die-termination merged output driver, 1.3Gb/s/pin operation at 1.36V and a column latency of 6 (CL6) is achieved
Keywords :
CMOS memory circuits; DRAM chips; electronic data interchange; 1.2 ns; 1.3 Gbit/s; 1.36 V; 1.7 ns; 2.9 ns; 512 Mbit; 8.4 ns; 90 nm; DDR3 SDRAM; column access; column latency; dual clock additive latency counter; multiplexed data transfer; CMOS technology; Clocks; Counting circuits; Delay; Flip-flops; Latches; Prefetching; Random access memory; SDRAM; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696092
