Title :
Power estimation technique for Reed-Muller logic circuits
Author :
Ye, Xien ; Gan, Xue ; Xia, Yinshui
Author_Institution :
Ningbo Univ., Ningbo
Abstract :
A power estimation technique for Reed-Muller logic circuits is proposed. Given the probability and transition density of input signals, AND/XOR gates are decomposed into a 2-input gate tree and its switching activity is calculated to estimate the power dissipation. Experimental results indicate that this proposed approach can well predict power dissipation of Reed-Muller logic without detail process information.
Keywords :
VLSI; logic circuits; logic design; logic gates; probability; 2-input gate tree; AND-XOR gates; Reed-Muller logic circuits; VLSI design; input signal transition density; power dissipation; power estimation technique; probability density; switching activity; Boolean functions; Capacitance; Clocks; Frequency; Logic arrays; Logic circuits; Logic testing; Power dissipation; Switching circuits; Terminology;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415589
