Adiabatic tree multipliers using modified booth algorithm

This paper presents an adiabatic tree multiplier based on modified Booth algorithm. All circuits including Booth encoders, partial product generators, and compressors are realized with DTGAL (dual transmission gate adiabatic logic) circuits. The energy loss of the proposed adiabatic circuits is compared with their corresponding PAL-2N and CMOS implementations. The proposed circuits are verified using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. The power consumption is greatly reduced since the energy transferred to large load capacitances is well recovered.