Title :
Exact Required Time Analysis Via False Path Detection
Author :
Kttkimoto, Y. ; Brayton, Robert K.
Author_Institution :
Department of Electrical Engineering and Computer Sciences, University of California
Keywords :
Automatic logic units; Circuit synthesis; Circuit testing; Computer networks; Delay; Logic testing; Network synthesis; Permission; Power dissipation; Timing;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597147
