DocumentCode
2567957
Title
A 10-bit pipeline ADC using 40-dB opamps and calibrated customized references
Author
Chen, Cheng ; Yuan, Jiren
Author_Institution
Lund Univ., Lund
fYear
2007
fDate
22-25 Oct. 2007
Firstpage
249
Lastpage
252
Abstract
A 10-bit pipeline A/D converter using low gain (les40 dB) operational amplifiers (opamps) is presented. Without interfering the normal analog-to-digital conversion, a continuous reference refreshing technique is exploited. This technique effectively reduces the gain requirement of opamp while the conversion speed is not compromised, allowing the use of simple cascode CMOS inverters. The compensation of finite gain of the opamp is made by using customized reference voltages that is calibrated periodically. The technique has been confirmed by intensive simulations. As a result of the relaxed opamp gain requirement, significant reduction in power consumption can be achieved.
Keywords
CMOS logic circuits; analogue-digital conversion; logic gates; operational amplifiers; pipeline arithmetic; CMOS inverters; analog-to-digital conversion; operational amplifiers; pipeline ADC; power consumption reduction; word length 10 bit; Bandwidth; CMOS technology; Calibration; Capacitors; Clocks; Energy consumption; Error correction; Information technology; Pipelines; Voltage; Calibration; finite opamp gain; pipeline A/D converter; reference refreshing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-4244-1132-0
Electronic_ISBN
978-1-4244-1132-0
Type
conf
DOI
10.1109/ICASIC.2007.4415614
Filename
4415614
Link To Document