A digital-background TIADC calibration architecture and a fast calibration algorithm for timing-error mismatch

Mismatches between sub-channels of time interleaved ADC (TIADC) include offset mismatch, gain mismatch and sampling-time mismatch, which degrade the performance of the system. A new TIADC system suitable for the digital-background measurement and calibration of these errors is proposed in this paper. Also, a fast interpolation algorithm aimed at the real time calibration of timing mismatch is discussed in great detail. The algorithm is easy to be implemented on chip. Simulation results show that the proposed system architecture and the algorithm can improve the spurious free dynamic range (SFDR) due to timing-error mismatch of the TIADC significantly.