Title :
A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS
Author :
Shimizu, Yukiyo ; Murayama, Shigeyuki ; Kudoh, K. ; Yatsuda, Hiromi ; Ogawa, Anna
Author_Institution :
Sony, Nagasaki
Abstract :
A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process. It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback amplifier. ENOB is 10.2b at a 0.7V supply and 11.0b at a 1.0V supply. The ADC consumes 30mW at 40MS/s
Keywords :
CMOS integrated circuits; analogue-digital conversion; feedback amplifiers; quantisation (signal); 0.7 V; 1.0 V; 12 bit; 7 bit; 90 nm; coarse quantizer; digital CMOS process; positive-feedback amplifier; subranging ADC; Capacitors; Circuits; Differential amplifiers; Energy consumption; High power amplifiers; Interpolation; Low voltage; Quantization; Sampling methods; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696120
