Title :
Interface Timing Verification Drives System Design Ajay J. Daga
Author :
Daga, Ajay J. ; Suaris, Peter R.
Author_Institution :
Interconnectix, a Mentor Graphics Business
Keywords :
Circuit simulation; Circuit synthesis; Delay; Design engineering; Information analysis; Integrated circuit interconnections; Intellectual property; Permission; Timing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597151
