• DocumentCode
    2567998
  • Title

    Interface Timing Verification Drives System Design Ajay J. Daga

  • Author

    Daga, Ajay J. ; Suaris, Peter R.

  • Author_Institution
    Interconnectix, a Mentor Graphics Business
  • fYear
    1997
  • fDate
    9-13 June 1997
  • Firstpage
    240
  • Lastpage
    245
  • Keywords
    Circuit simulation; Circuit synthesis; Delay; Design engineering; Information analysis; Integrated circuit interconnections; Intellectual property; Permission; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1997. Proceedings of the 34th
  • Conference_Location
    Anaheim, CA, USA
  • ISSN
    0738-100X
  • Print_ISBN
    0-7803-4093-0
  • Type

    conf

  • DOI
    10.1109/DAC.1997.597151
  • Filename
    597151
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2567998