Title :
A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS
Author :
Bogner, P. ; Kuttner, F. ; Kropf, Carsten ; Hartig, T. ; Burian, M. ; Eul, H.
Author_Institution :
Infineon, Villach
Abstract :
A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; 0.13 micron; 14 bit; charge compensation; digital CMOS process; gain errors; matching errors; operational amplifiers; self-calibrated pipelined ADC; CMOS process; CMOS technology; Calibration; Capacitors; Circuits; Energy consumption; High-resolution imaging; Intersymbol interference; Low voltage; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696123
