Title :
Implementing Globally Asynchronous Locally Synchronous processor pipeline on commercial synchronous FPGAs
Author :
Farouk, Hala A. ; El-Hadidi, Mahmoud T.
Author_Institution :
Comput. Eng. Dept., Arab Acad. for Sci. & Technol., Alexandria, Egypt
Abstract :
In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages´ delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show that the GALS approach increase the pipeline throughput by 21% and reduces the power consumption by 26.8%.
Keywords :
field programmable gate arrays; microprocessor chips; commercial synchronous FPGA; globally asynchronous locally synchronous processor pipeline; globally-asynchronous locally-synchronous pipelined processor; pipelined accumulator-based processor; Circuits; Clocks; Decoding; Delay; Energy consumption; Fabrics; Field programmable gate arrays; Libraries; Pipelines; Telecommunication computing; globally asynchronous locally synchronous; pipelined instruction-set processor; synchronous FPGA;
Conference_Titel :
Telecommunications (ICT), 2010 IEEE 17th International Conference on
Conference_Location :
Doha
Print_ISBN :
978-1-4244-5246-0
Electronic_ISBN :
978-1-4244-5247-7
DOI :
10.1109/ICTEL.2010.5478856
