Title :
A 15mW 0.2mm/sup 2/ 50MS/s ADC with wide input range
Author :
Hee-Cheol Choi ; Ju-Wha Kim ; Sang-Min Yoo ; Kang-Jin Lee ; Tae-Hwan Oh ; Mi-Jung Seo ; Jae-Whui Kim
Author_Institution :
Samsung, Yongin
Abstract :
A 10b 50MS/s pipelined ADC, implemented in a 0.13mum CMOS process, consumes of 15mW and occupies an active die area of 0.2mm2 . In the prototype ADC, a high-to-low analog level-shifting SHA is proposed to deal with a wide input range of 2VPP differential. A PVT-insensitive bias generator is employed for low voltage operation. The measured DNL and INL are plusmn0.17LSB and plusmn0.16LSB, respectively
Keywords :
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; pipeline processing; sample and hold circuits; 0.13 micron; 10 bit; 15 mW; CMOS process; PVT-insensitive bias generator; pipelined ADC; sample and hold amplifiers; Circuits; Digital multimedia broadcasting; Digital video broadcasting; Dynamic range; Energy consumption; Sampling methods; Satellite broadcasting; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696124
