Title :
A 9.95 to 11.1Gb/s XFP transceiver in 0.13/spl mu/m CMOS
Author :
Kenney, Jack ; Dalton, Declan ; Eskiyerli, M. ; Evans, E. ; Hilton, Benjamin ; Hitchcox, D. ; Kwok, T. ; Mulcahy, D. ; McQuilkin, C. ; Reddy, Veerababu ; Selvanayagam, S. ; Shepherd, Peter ; Titus, Ward ; DeVito, Larry
Author_Institution :
Analog Devices, Somerset, NJ
Abstract :
A 9.95 to 11.1 Gb/s transceiver in 0.13mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL to exceed SONET jitter specifications. A half-rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 9.5 inches of FR4 is equalized resulting in random jitter(rms) under 4mUI. Power consumption is 800mW
Keywords :
CMOS integrated circuits; SONET; delay lock loops; jitter; optical receivers; optical transmitters; phase detectors; phase locked loops; printed circuit design; transceivers; 0.13 micron; 800 mW; 9.5 in; 9.95 to 11.1 Gbit/s; CDR; CMOS; FR4; SONET jitter specifications; XFP modules; dispersion jitter; dual-loop DLL; dual-loop PLL; half-rate binary phase detector; random jitter; serializer; transceiver; Bandwidth; Charge pumps; Clocks; Detectors; Frequency conversion; Jitter; Optical receivers; Phase detection; Phase locked loops; Transceivers;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696127
