Low jitter design for ring oscillator in Serdes

Author

Xiao, Lei ; Liu, Wei ; Yang, Lianxing

Author_Institution

Fudan Univ., Shanghai

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

307

Lastpage

310

Abstract

A new configuration of delay cell used in voltage controlled oscillators is presented. Jitter comparison between source-coupled differential delay cell and the proposed voltage-controlled-oscillator configuration is given. Loop parameter based on low-jitter optimization in PLL is also introduced. A low-jitter 1.25 GHz SerDes is implemented in a 0.35 mum standard 2P3M CMOS process. The result shows that, RJ rms (random jitter) of high speed series output is 2.3 ps (0.0015UI) and RJ (1sigma) is 0.0035 UI. Phase noise measure shows -120 dBc/Hz at 100 kHz.

Keywords

CMOS integrated circuits; delay-differential systems; jitter; phase locked loops; voltage-controlled oscillators; PLL; SerDes; frequency 1.25 GHz; loop parameter; low jitter design; low-jitter optimization; random jitter; ring oscillator; size 0.35 mum; source-coupled differential delay cell; standard 2P3M CMOS process; voltage controlled oscillators; CMOS process; Delay; Jitter; Noise measurement; Phase locked loops; Phase noise; Ring oscillators; Velocity measurement; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415628

Filename

4415628