A 1.2V low-jitter PLL for UWB

This paper describes a 1.2-V, low-power and low jitter PLL applied to UWB and designed in a 0.13 mum CMOS technology. The PLL is designed with a PFD with excellent high-frequency performance, low-voltage noise-suppressed charge pump, classic symmetrical-load differential delay cells and duty-buffer in which the duty-cycle is 50%. System stability verification and spice simulation show that the PLL is stable and the jitter is only lps (TT@75degC). The power is only 4 mw(TT @75 degC) when the oscillating frequency is 528 MHZ.