Title :
A 1.2V low-jitter PLL for UWB
Author :
Xiao, Manxia ; Li, Ning ; Ye, Fan ; Ren, Junyan
Author_Institution :
Fudan Univ., Shanghai
Abstract :
This paper describes a 1.2-V, low-power and low jitter PLL applied to UWB and designed in a 0.13 mum CMOS technology. The PLL is designed with a PFD with excellent high-frequency performance, low-voltage noise-suppressed charge pump, classic symmetrical-load differential delay cells and duty-buffer in which the duty-cycle is 50%. System stability verification and spice simulation show that the PLL is stable and the jitter is only lps (TT@75degC). The power is only 4 mw(TT @75 degC) when the oscillating frequency is 528 MHZ.
Keywords :
CMOS integrated circuits; jitter; phase locked loops; ultra wideband communication; CMOS technology; PFD; SPICE; UWB; classic symmetrical-load differential delay cells; duty-buffer; low-jitter PLL; low-voltage noise-suppressed charge pump; oscillating frequency; system stability verification; Charge pumps; Circuits; Clocks; Delay; Jitter; Leakage current; Phase frequency detector; Phase locked loops; Ring oscillators; Voltage-controlled oscillators;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415632
