Two-dimensional layout compaction by simulated annealing

The authors study the two-dimensional compaction problem or VLSI layouts. They present an algorithm for the two-dimensional compaction problem. Compaction is carried out simultaneously in both x and y directions. The problem model is constraint-based. The compactor does not rely on a given initial placement. In fact, it fully utilizes freedom to place blocks and also uses the technique of simulated annealing to examine layout solutions one after another in its search for an optimal layout solution. To speed up the computations, a powerful approximation scheme is also introduced. The simulated annealing layout compactor has been implemented and tested on some problems from the literature. The experimental results indicate that the proposed compaction algorithm is quite effective.<>