Navigating Core Assisted Helper Threaded Prefetching

Memory system of chip multi-threaded processors (CMT) suffers greater than ever before because of memory latencies brought by overloaded memory accessing requests. Data prefetching using helper threads has been proved to be an effective approach to tolerate memory latencies by past researches. However, as the sum total of threads increase, simultaneously occupying available idle thread context in each core, there exist the possibility in which resource contention happen frequently among helper threads and main threads. This paper proposes to devise the helper threaded prefetching utilizing independent navigating core, where helper thread runs, for each processor core. With this method, helper thread can be freed from resource limitation and take advantage of helper threaded prefetching strategy, consequently promoting the holistic performance of chip multi-threaded processors. Experimenting results demonstrate that by using navigating core helper threaded prefetching can well improve instruction per cycle and remarkably reduce miss ratio of delinquent loads compared with a traditional helper threaded prefetching strategy.