Architecture for a non-deterministic simulation machine

Author

Bumble, Marc ; Coraor, Lee

Author_Institution

Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA

Volume

2

fYear

1998

fDate

13-16 Dec 1998

Firstpage

1599

Abstract

Causality constraints of random discrete simulation make parallel and distributed processing difficult. Methods of applying reconfigurable logic to implement and accelerate simulation service event queues are presented which process simulation events at a rate of one event per 80 ns. The event generator presented in our previous work (Bumble and Coraor, 1998) is also capable of sustaining the 80 ns clock rate, providing overall speedup rates which depend on the software comparison scenario. The software comparison cited in this work provides a 2-order-of-magnitude speedup. The speedup factor varies with the size of the software event queue. Field programmable gate arrays (FPGAs) are used to implement and test the service queue design

Keywords

causality; computer architecture; discrete event simulation; field programmable gate arrays; queueing theory; software performance evaluation; special purpose computers; 80 ns; FPGA; causality constraints; clock rate; distributed processing; event generator; field programmable gate arrays; nondeterministic simulation machine architecture; parallel processing; random discrete simulation; reconfigurable logic; simulation service event queues; software comparison scenario; software event queue size; speedup factor; Acceleration; Clocks; Computational modeling; Discrete event simulation; Field programmable gate arrays; Hardware; Reconfigurable logic; Statistical distributions; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Conference Proceedings, 1998. Winter

Conference_Location

Washington, DC

Print_ISBN

0-7803-5133-9

Type

conf

DOI

10.1109/WSC.1998.746035

Filename

746035