Spare processor allocation for fault tolerance in torus-based multicomputers

Author

Bae, Myung M. ; Bose, Bella

Author_Institution

Dept. of Comput. Sci., Oregon State Univ., Corvallis, OR, USA

fYear

1996

fDate

25-27 Jun 1996

Firstpage

282

Lastpage

291

Abstract

Some fault-tolerant architectures use the spare nodes or links to replace the faulty components. This paper gives solutions to spare processor placement problem for torus based networks. Optimal 1-hop spare processor placement methods for multi-dimensional tori and t-hop placement methods for 2D tori are described. In the presence of node failures, a system reconfiguration scheme using spare nodes is also given

Keywords

computer network reliability; fault tolerant computing; multiprocessing systems; multiprocessor interconnection networks; processor scheduling; reconfigurable architectures; reliability; fault tolerance; fault-tolerant architectures; multi-dimensional tori; node failures; spare processor allocation; system reconfiguration scheme; torus based networks; torus-based multicomputers; Circuit faults; Computer architecture; Computer science; Concurrent computing; Fault tolerance; Integrated circuit interconnections; Linear code; Peer to peer computing; Switching circuits; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault Tolerant Computing, 1996., Proceedings of Annual Symposium on

Conference_Location

Sendai

ISSN

0731-3071

Print_ISBN

0-8186-7262-5

Type

conf

DOI

10.1109/FTCS.1996.534613

Filename

534613

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2568493