High-voltage NMOS in 0.5 μm CMOS technology for fast switching applications

Author

Santos, Pedro M. ; Quaresma, H. ; Silva, A.P. ; Lança, M.

Author_Institution

Instituto de Telecommunicacoes, Lisboa, Portugal

Volume

1

fYear

2003

fDate

9-11 June 2003

Firstpage

506

Abstract

This paper describes high-voltage NMOS devices implementation in a deep submicron 0.5 μm CMOS process, only resorting to design layout strategies. Experiments show the viability of using the Gate-Shift technique to improve devices breakdown voltage to circa 29 V, while other electrical parameters are kept at reasonable values. From the availability of these high voltage NMOS transistors it can be concluded that designers can resort to last generation CMOS processes to develop cost smart power integrated circuits.

Keywords

CMOS integrated circuits; power MOSFET; power integrated circuits; switching circuits; 0.5 mum; CMOS process; Gate-Shift technique; NMOS transistors; breakdown voltage; complementary metal-oxide-semiconductor; design layout strategies; electrical parameters; fast switching applications; high-voltage NMOS devices implementation; smart power integrated circuits; CMOS process; CMOS technology; Degradation; Epitaxial layers; Fabrication; Foundries; Implants; Ion implantation; MOS devices; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics, 2003. ISIE '03. 2003 IEEE International Symposium on

Print_ISBN

0-7803-7912-8

Type

conf

DOI

10.1109/ISIE.2003.1267302

Filename

1267302