Design and optimization of highly linear CMOS low noise amplifiers via geometric programming

Linearity is an important measurement for the performance of a CMOS low noise amplifier (LNA). The high computational cost required in the linearity simulation, however, constitutes a major bottleneck in the design verification stage. In this paper, we develop a novel and systematic geometric programming (GP)-based approach for the optimized design of a highly linear CMOS LNA, subject to the minimization of the noise factor. Experiments confirm the remarkable efficacy and accuracy of the proposed design flow against traditional simulators.