Title :
A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects
Author :
Kromer, C. ; Sialm, G. ; Menolfi, Christian ; Schmatz, Martin ; Ellinger, F. ; Jackel, Heinz
Author_Institution :
ETH Zurich
Abstract :
A CDR for source-synchronous high-density link applications receives 25Gb/s at a BER of <10-12. The CDR is a first-order bang-bang topology employing a phase interpolator, linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter. The core CDR circuit occupies 0.09mm2 and consumes 98mW from a 1.1V supply
Keywords :
CMOS integrated circuits; clocks; integrated circuit interconnections; nanotechnology; phase detectors; synchronisation; 1.1 V; 25 Gbit/s; 90 nm; 98 mW; CDR; CMOS; analog filter; bang-bang topology; digital loop filter; high-density interconnects; limiter circuit; phase detector; phase interpolator; source-synchronous high-density link; Clocks; Counting circuits; Digital filters; Frequency conversion; Phase detection; Phase frequency detector; Pipelines; Pulse measurements; Switches; Topology;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696174
