DocumentCode :
2568926
Title :
A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter
Author :
Perrott, M.H. ; Yunteng Huang ; Baird, R.T. ; Garlepp, B.W. ; Ligang Zhang ; Hein, J.P.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA
fYear :
2006
fDate :
6-9 Feb. 2006
Firstpage :
1276
Lastpage :
1285
Abstract :
A CDR comprises a Hogge detector and a 1st-order DeltaSigmaADC, and uses a hybrid analog/digital loop filter to enhance integration and allow bandwidth tuning over a wide range of data rates from 155Mb/s to 2.7Gb/s. The CDR exceeds SONET performance at relevant data rates and generates 1.2psrms jitter at 2.5Gb/s
Keywords :
CMOS integrated circuits; analogue-digital conversion; clocks; integrated circuit design; phase detectors; synchronisation; 0.155 to 2.7 Gbit/s; 0.25 micron; Hogge detector; bandwidth tuning; delta-sigma ADC; hybrid analog-digital loop filter; multirate CMOS CDR; Band pass filters; Bandwidth; Capacitors; Circuits; Digital filters; Frequency; Phase locked loops; Topology; Varactors; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0079-1
Type :
conf
DOI :
10.1109/ISSCC.2006.1696175
Filename :
1696175
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2568926
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