Title :
Improving CDR Performance via Estimation
Author :
Haechang Lee ; Bansal, Ankur ; Frans, Yohan ; Zerbe, Jared ; Sidiropoulos, S. ; Horowitz, Mark
Author_Institution :
Stanford Univ., CA
Abstract :
A dual-loop CDR can be viewed as a simple phase-estimator. Different estimators can be built by changing the phase DAC control logic. Three different 0.13mum estimators for a 3Gb/s serial link are presented. These estimators address dual-loop CDR limitations including lock time, frequency range, and jitter tolerance in non-mesochronous systems
Keywords :
digital phase locked loops; digital-analogue conversion; phase detectors; timing jitter; 0.13 micron; 3 Gbit/s; dual-loop CDR; frequency range; jitter tolerance; lock time; nonmesochronous systems; phase DAC control logic; phase estimator; serial link; Bandwidth; Clocks; Degradation; Delay; Delta modulation; Filtering; Frequency; Phase estimation; Phase modulation; Timing jitter;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696177
