CMOS Anti-Self-Biasing effect and its implication in analog/RF circuit design

Large-signal power performance of RF CMOS devices is investigated. Uncommon DC current variation with input power level under large-signal operation of the devices, which is defined as "anti-self-biasing effect", is firstly reported in this paper. The anti-self-biasing effect, different from the commonly observed self-biasing effect in bipolar junction transistors (BJTs) is found to be dependent on DC bias voltages. At low VD bias, when VG bias is high, the drain current decreases when increasing the input power. When VG bias is low, the drain current increases with the increase input RF power level. This unique phenomenon is explained with dynamic load lines and its implication to analog and RF circuit design is discussed. By optimizing DC bias, significantly improved large-signal power performances of the RF CMOS devices are obtained.