Title :
A 3.2Gb/s Semi-Blind-Oversampling CDR
Author :
van Ierssel, Marcus ; Sheikholeslami, Ali ; Tamura, H. ; Walker, W.W.
Author_Institution :
Toronto Univ., Ont.
Abstract :
A hybrid CDR increases jitter tolerance of a phase-tracking CDR by a factor of 32 at low frequencies, while maintaining the high-frequency jitter tolerance of a 5times blind-oversampling CDR. Measurements on a 0.11 mum CMOS test chip at 2.4Gb/s confirm a 200Ulpp jitter tolerance at 200kHz. At 2.4Gb/s, the chip consumes 180mW from a 1.2V supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; phase locked loops; synchronisation; timing jitter; 0.11 micron; 1.2 V; 180 mW; 2.4 Gbit/s; 3.2 Gbit/s; CMOS chip; hybrid CDR; jitter tolerance; phase-tracking CDR; semi-blind oversampling; Clocks; Frequency; Jitter; Laboratories; Low pass filters; Phase estimation; Spread spectrum communication; Tracking loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696178
