Title :
Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache
Author :
Tam, Simon ; Leung, J. ; Limaye, Rhishikesh ; Choy, S. ; Vora, Sujal ; Adachi, Masakazu
Author_Institution :
Intel, Santa Clara, CA
Abstract :
The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for <11ps global clock skew in a 435mm2 die. The cache and control sections contain 2 primary clock domains and 11 clock spines. A pipelined de-skew logic tolerant to inter-domain clock uncertainties manages the core and cache/control data communication
Keywords :
cache storage; clocks; microprocessor chips; 16 MByte; L3 cache; clock distribution; clock domains; clock generation; clock spines; data communication; dual-core Xeon processor; global clock skew; pipelined de-skew logic; CMOS process; Clocks; Delay; Frequency; Fuses; Inverters; Libraries; Logic; Topology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696202
