Title :
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor
Author :
Thomson, Michael G R ; Restle, Phillip J. ; James, Norman K.
Author_Institution :
IBM, Yorktown Heights, NY
Abstract :
Microprocessor global clock distribution networks use long buffered wires where reflections can be significant. Using accurate transmission-line models and optimization, these reflection effects can be exploited to improve clock-distribution characteristics. The clock distribution network of the P0WER6 microprocessor is designed to run at frequencies exceeding 5GHz using only inverters and transmission lines and is capable of on-the-fly duty-cycle correction
Keywords :
clocks; integrated circuit design; integrated circuit interconnections; microprocessor chips; 5 GHz; POWER6 microprocessor; buffered wires; inverters; microprocessor global clock distribution networks; on-the-fly duty-cycle correction; transmission-line models; transmission-line optimization; Circuit testing; Clocks; Degradation; Frequency; Impedance; Microprocessors; Power transmission lines; Reflection; Timing; Wire;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696203
