Title :
Distributed Loss Compensation for Low-latency On-chip Interconnects
Author :
Jose, Anup P. ; Shepard, Kenneth L.
Author_Institution :
Columbia Univ., New York, NY
Abstract :
The use of distributed loss compensation for on-chip interconnects is discussed. Results are presented for a 14mm 3Gb/s on-chip link in 0.18mum CMOS with a measured latency of 12.1ps/mm and an energy dissipation of 2pJ/b with a BER<10-14. A 3times improvement in power consumption and a 1.5times improvement in latency over an optimally-repeated RC line is demonstrated
Keywords :
CMOS integrated circuits; RC circuits; integrated circuit design; integrated circuit interconnections; 14 mm; 3 Gbit/s; BER; CMOS; RC line; distributed loss compensation; energy dissipation; on-chip interconnects; power consumption; Attenuation; Bandwidth; Capacitance; Degradation; Delay; Energy efficiency; Frequency; Transconductors; Transmission lines; Wires;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696207
