Hardware-in-the-loop simulation testbed design of FCS-VP based on statemate

This paper presents a novel design approach of virtual prototype of flight control system of UAV based on Statemate technology, and introduces the process designing a hierarchical function model of FCS with Activity-Charts in detail, and at the end of this paper a hardware-in-the-loop simulation testbed is built to verify performances of FCS-VP of UAV in various conditions like that GPS signals are lost and then resumed after some seconds. Results of experiments show that, without any loss of system performance, a mini-scale, high-speed real time complex embedded hybrid system testbed can be made to measure control system operation performance with the lowest investment. It is obviously that the research method for the engineering implementation of systems and the application of VP in control systems is much worthy of applying and generalizing.