Optimizing approach of spiral inductors for Si-Based ICs

A particular optimizing approach that aims at the modeling, analysis and design of integrated spiral inductors is addressed in this paper. The novel optimizing approach is based on analyzing the tapered inductor and symmetric inductor. With the optimizing approach, the advantages of tapered inductor and symmetric spiral inductor are combined and the Q-value and differential character of the inductor are enhanced remarkably. This optimization approach especially suits the requirements of high performance and makes entire differential VCO into a high performance spiral inductor. The new type inductor has been simulated and verified with ASITIC. This optimized design selects the representative monolayer square spiral inductor as the test object, the operating frequency is 2.439 GHz, and the chip area maximum value definition is 250 times 250 um².