Title :
A 160kgate 4.5kB SKRAM H.264 video decoder for HDTV applications
Author :
Lin, C.C. ; Guo, J.I. ; Chang, H.C. ; Yang, Y.C. ; Chen, J.W. ; Tsai, M.C. ; Wang, J.S.
Author_Institution :
National Chung-Cheng Univ., Chia-Yi
Abstract :
Through both algorithmic and architectural optimization, the H.264 video decoder dissipates 320mW at 1.8V when operating at 120MHz for HD1080 (1920times1088 at 30frames/s). The die contains 160kgates 4.5kB memory and occupies 2.9times2.9mm2 in 0.18mum CMOS
Keywords :
CMOS memory circuits; SRAM chips; high definition television; video coding; 0.18 micron; 1.8 V; 120 MHz; 320 mW; 4.5 kByte; CMOS memory circuit; H.264 video decoder; HDTV applications; SRAM video decoder; algorithmic optimization; architectural optimization; Application specific integrated circuits; Automatic voltage control; Bandwidth; CMOS technology; Codecs; Decoding; Energy consumption; HDTV; Hardware; MPEG 4 Standard;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696214
