A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter

Author

Yin, Yong-sheng ; Gao, Ming-Lun ; Deng, Hong-Hui ; Liang, Shang-Quan ; Liu, Cong

Author_Institution

Hefei Univ. of Technol., Hefei

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

703

Lastpage

706

Abstract

A 14-bit, 130MSPS DAC with 2times FIR interpolation filter simulated in a 0.35 mum CMOS process is described in this paper. The DAC adopts segmented current-steering structure, which combines the characteristic of unit current DAC and the binary weighted DAC to get the balance between area and performance. A 2times FIR interpolation filter is introduced to reduce the complexity of analog reconstruction filter following the DAC. Key circuits and simulation results are presented. The results show that this DAC can deliver up to 20 mA current into a 50Omega load. Power dissipation with 3.3 V supply is 286 mW at 200 MHz DAC update rate. The INL is plusmn3.5LSB, and DNL is plusmn 2.0LSB. SFDR is 76 dB at 100 MSPS and 50 MHz output frequency.

Keywords

CMOS integrated circuits; FIR filters; digital-analogue conversion; FIR interpolation filter; analog reconstruction filter; binary weighted DAC; current-steering CMOS; digital-analogue converters; frequency 200 MHz; frequency 50 MHz; power 286 mW; resistance 50 ohm; size 0.35 mum; unit current DAC; voltage 3.3 V; word length 14 bit; CMOS process; CMOS technology; Decoding; Finite impulse response filter; Interpolation; Phase locked loops; Resistors; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415728

Filename

4415728