A high-performance memory storage architecture for MP@HL MPEG2 decoder chip

A major bottleneck of MP@HL MPEG-2 decoder is the memory bandwidth. It is important to improve the utilization ratio of the memory bandwidth in MPEG2 decoder. To realize it, a new memory storing architecture is proposed in this paper. Since the number of overhead cycles needed for row-activations in SDRAM can be minimized, the memory bandwidth can be improved significantly. Compared with the linear translation, our experimental results show that the proposed architecture can reduce about 90% of row activations and 60% of the cycles needed by the decoder. It can easily meet MP@HL decoder bandwidth requirement without cache used.