Title :
A 240ps 64b carry-lookahead adder in 90nm CMOS
Author :
Kao, S. ; Zlatanovici, R. ; Nikolic, B.
Author_Institution :
California Univ., Berkeley, CA
Abstract :
A 64b adder with a single-execution cycle time of 250ps is fabricated in a 90nm CMOS technology. The adder is designed using an energy-delay optimization framework that can rapidly optimize different microarchitectures in the energy-delay space. The microarchitecture with the lowest delay, a sparse radix-4 Ling parallel prefix tree, is chosen. The carry tree uses footless domino logic to minimize delay while the non-critical paths use minimum-size static logic to reduce energy. The adder consumes 311mW from a 1V supply
Keywords :
CMOS logic circuits; adders; carry logic; logic design; 1 V; 250 ps; 311 mW; 64 bit; 90 nm; CMOS technology; carry tree; carry-lookahead adder; footless domino logic; sparse radix-4 Ling parallel prefix tree; static logic; Added delay; Adders; CMOS technology; Capacitance; Circuit synthesis; Circuit testing; Design optimization; Energy efficiency; Equations; Microprocessors;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696230
