• DocumentCode
    25701
  • Title

    An 80\\times Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-

  • Author

    Horng-Yuan Shih ; Sheng-Kai Lin ; Po-Shun Liao

  • Author_Institution
    Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
  • Volume
    23
  • Issue
    8
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    1528
  • Lastpage
    1533
  • Abstract
    An analog-implemented time-difference amplifier applied for coarse-fine time-to-digital converters is presented in this paper. Implemented in 0.18-μm CMOS process, a time difference within 225 ps can be amplified 80× linearly under maximum frequency of 25 MHz. Measured maximum gain error is 4.1%. Measured output rms jitter is 84.5 ps under gain of 80×. The time amplifier consumes 1.7 mW under supply voltage of 1.8 V.
  • Keywords
    CMOS integrated circuits; amplifiers; analogue integrated circuits; convertors; CMOS; analog-implemented time-difference amplifier; delay-line-based coarse-fine time-to-digital converters; frequency 25 MHz; power 1.7 mW; size 0.18 mum; time 225 ps; time 84.5 ps; voltage 1.8 V; Delays; Detectors; Gain measurement; Generators; Jitter; Measurement uncertainty; Noise; Coarse-fine time-to-digital converter (TDC); TDC; time-difference amplifier (TA);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2343244
  • Filename
    6877702
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=25701