Title :
Clip: An Optimizing Layout Generator For Two-dimensional Cmos Cells
Author :
Gupta, Avaneendra ; Hayes, John P.
Author_Institution :
University of Michigan
Keywords :
CMOS technology; Circuit synthesis; Circuit testing; Computer architecture; Laboratories; Linear programming; Minimization; Routing; Semiconductor device modeling; Wire;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-7803-4093-0
DOI :
10.1109/DAC.1997.597190
