Design and VLSI implementation of a security ASIP

Author

Lu, Ronghua ; Xiaoyang Zeng ; Han, Jun ; Gu, Yehua ; Mai, Lang

fYear

2007

fDate

22-25 Oct. 2007

Firstpage

866

Lastpage

869

Abstract

The ASIP, which features the high efficiency of ASIC coprocessor and the flexibility of general purpose processor, has and will have popular application in Information security domain. This paper presents a new design and VLSI architecture of security ASIP for RSA/ECC of cryptographic algorithms. By adopting the special instructions and computing unit, the proposed 32-bit RISC processor achieves the goal of high-speed and low-cost. Based on TSMC 0.25 mum standard CMOS technology, the core circuit of this security ASIP has only about 28k gates, and a max frequency of 150 MHz , under which only 200 ms is required when the security ASIP excutes a 1024-bit RSA.

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; coprocessors; cryptography; reduced instruction set computing; ASIC coprocessor; CMOS technology; Information security; RISC processor; RSA/ECC cryptographic algorithms; VLSI; general purpose processor; security ASIP; Algorithm design and analysis; Application specific integrated circuits; Application specific processors; CMOS technology; Computer aided instruction; Computer architecture; Coprocessors; Elliptic curve cryptography; Information security; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2007. ASICON '07. 7th International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4244-1132-0

Electronic_ISBN

978-1-4244-1132-0

Type

conf

DOI

10.1109/ICASIC.2007.4415768

Filename

4415768