A novel baseband-processor for LF RFID tag

A novel baseband-processor for LF RFID tag compatible with ISOl 1784/11785 is presented. An asynchronous method for data demodulation is proposed to solve the clock halting problem during 100% ASK modulation mode and a new command decoder is designed to increase command decoding speed. Other low-power techniques, such as power management, module reuse and architecture optimization are also implemented to enhance tag interference immunity and to reduce chip area as well as power consumption. The processor is verified on Xilinx Virtex-II Pro real-time verification platform and the results prove the completeness of its designed functionality and its low power consumption. The chip is fabricated using a 0.18 mum 2P4M CMOS standard process with the die area of 300 mum times 300 mum.