Title :
A Clock Duty-Cycle Correction and Adjustment Circuit
Author :
Humble, James S. ; Zabinski, Patrick J. ; Gilbert, Barry K. ; Daniel, Erik S.
Author_Institution :
Mayo Clinic, Rochester, MN
Abstract :
A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is demonstrated. The output duty cycle is selectable from 41.25% to 58.75% in 1.25% increments. The circuitry is integrated into a clock-distribution chip which provides 10 identical outputs
Keywords :
clocks; 0.5 to 6 GHz; adjustment circuit; clock duty-cycle correction circuit; clock-distribution chip; input duty cycles; output duty cycle; Charge pumps; Circuits; Clamps; Clocks; Digital communication; Diodes; Frequency; Jitter; Parasitic capacitance; Voltage control;
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0079-1
DOI :
10.1109/ISSCC.2006.1696273
