A parameter extraction technique for heterojunction bipolar transistors

A technique useful for parameter extraction of heterojunction bipolar transistors (HBTs) is presented. The technique makes use of a tee equivalent circuit based on the physical operation of the device. The technique uses the device f/sub T/, determined by extrapolation of the device h parameters, to establish the total emitter-to-collector delay time from the experimental data. This information is used to establish an equation that is used to constrain the circuit elements, thereby facilitating the parameter extraction procedure. The technique is easily implemented using commercially available computer software. The technique is demonstrated by application to state-of-the-art InGaAs/AlInAs/InP HBTs.<>