Author :
Kanno, Yusuke ; Mizuno, Hiroyuki ; Yasu, Yoshihiko ; Hirose, Kenji ; Shimazaki, Yasuhisa ; Hoshi, Tadashi ; Miyairi, Yujiro ; Ishii, Toshifumi ; Yamada, Tetsuya ; Irita, Takahiro ; Hattori, Toshihiro ; Yanagisawa, Kazumasa ; Irie, Naohiko
Abstract :
Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor
Keywords :
leakage currents; logic design; low-power electronics; microprocessor chips; mobile handsets; 90 nm; fine-grained clock gating; fine-grained power gating; hierarchical power distribution; leakage currents; multiCPU processor; power tree; single-chip 3G cellular phone processor; Cellular phones; Clocks; Digital signal processing; Energy management; Leakage current; Power distribution; Repeaters; Signal restoration; Tree data structures; Ultra large scale integration;
