DocumentCode :
2570806
Title :
A Test Synthesis Approach To Reducing Ballast Dft Overhead
Author :
Chang, Douglas ; Lee, Mike Tien-Chien ; Marek-Sadowska, Malgorzata ; Aikyo, Takashi ; Cheng, Kwang-Ting
Author_Institution :
Univ. of CaIifornia
fYear :
1997
fDate :
9-13 June 1997
Firstpage :
466
Lastpage :
471
Keywords :
Automatic test pattern generation; Automatic testing; Circuit synthesis; Circuit testing; Electronic ballasts; Flip-flops; Hardware; Permission; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the 34th
Conference_Location :
Anaheim, CA, USA
ISSN :
0738-100X
Print_ISBN :
0-7803-4093-0
Type :
conf
DOI :
10.1109/DAC.1997.597193
Filename :
597193
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2570806
