DocumentCode :
2570813
Title :
A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs
Author :
Petrescu, Violeta ; Pelgrom, Marcel ; Veendrick, Harry ; Pavithran, Praveen ; Wieling, Jean
Author_Institution :
Philips Res. Labs., Eindhoven
fYear :
2006
fDate :
6-9 Feb. 2006
Firstpage :
2220
Lastpage :
2229
Abstract :
A fully integrated signal-integrity self-test concept is implemented in a 90nm CMOS process. The outputs of different analog monitors are locally converted to digital form and then transported through a test-compatible scan chain. The temperature monitor has 4b resolution. The supply-noise monitor detects 10ps-wide pulses of 20mV. The total area overhead is <0.1%
Keywords :
CMOS integrated circuits; boundary scan testing; built-in self test; integrated circuit testing; nanoelectronics; 20 mV; 90 nm; nanometer CMOS integrated circuits; signal-integrity self-test; supply-noise monitor; temperature monitor; test-compatible scan chain; Built-in self-test; CMOS digital integrated circuits; Circuit noise; Debugging; Diodes; Power measurement; Power supplies; Semiconductor device noise; Temperature; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
1-4244-0079-1
Type :
conf
DOI :
10.1109/ISSCC.2006.1696283
Filename :
1696283
Link To Document :
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