Author :
Meng, Tao ; Zhang, Yan ; Dai, Zi-bin
Abstract :
Adopting Coarse-grain reconfigurable technology, 8 reconfigurable cells are designed. With these reconfigurable cells, 30 block ciphers, which include RijndaeL DES, TWOFISH, IDEA, can be realized; Separated data and sub-key register files are designed, and the Auto-Increment Access Mode is put forward. With this mode, the size of instruction RAM can be reduced a lot, and the flexibility of processing is also increased; Five-stage pipelines of whole architecture and two-stage pipelines of function cell are designed, and when it is fabricated on 0.18 um CMOS cells, core work-frequency is 312.5 MHz; Bypassing is adopted to resolve data hazards, and Speculation is adopted to resolve control hazards; Auto-Copied Threading Mode is put forward to improve threading-Level Parallelism. In this mode, speeds processing Rijndael, DES, IDEA are 1379.2 Mbps, 800 Mbps, 563.3 Mbps.
Keywords :
coprocessors; cryptography; pipeline processing; random-access storage; CMOS cells; DES; IDEA; RijndaeL; TWOFISH; autocopied threading mode; autoincrement access mode; coarse-grain reconfigurable technology; instruction RAM; mix-clustered block cipher coprocessor; reconfigurable cells; sub-key register files; threading-level parallelism; Application specific integrated circuits; Arithmetic; CMOS process; Coprocessors; Field programmable gate arrays; Hazards; Logic; Pipelines; Registers; Size control;
