Title :
A unified IDCT architecture for multi-standard video codecs
Author :
Bingbo, Li ; Ding, Zhang ; Jian, Fang ; Lianghao, Wang ; Ming, Zhang
Author_Institution :
Zhejiang Univ., Hangzhou
Abstract :
A unified 2-D IDCT architecture for multi-standard video codecs is proposed in this paper. The architecture is based on row-column decomposition method. A unified 4-state pipelined architecture is employed to implement the 1-D transform. Parallel register array is used to realize the transpose operation. The proposed architecture has a throughput of 3.2 pixels/cycle. Experiment results show that the proposed design achieves HDTV 1080i video processing requirement when operated at 30 MHz.
Keywords :
discrete cosine transforms; high definition television; pipeline processing; video codecs; 1-D transform; HDTV 1080i video processing requirement; frequency 30 MHz; multistandard video codecs; parallel register array; pipelined architecture; row-column decomposition method; unified 2-D IDCT architecture; Automatic voltage control; Discrete cosine transforms; Flowcharts; HDTV; Hardware; MPEG 4 Standard; Throughput; Transform coding; Video codecs; Video compression;
Conference_Titel :
ASIC, 2007. ASICON '07. 7th International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4244-1132-0
Electronic_ISBN :
978-1-4244-1132-0
DOI :
10.1109/ICASIC.2007.4415792
