System-on-chip design for a statistical decoder

In this paper, we propose a system-on-chip software hardware co-design for a statistical decoder. We use the context-based adaptive binary arithmetic decoder (CABAC decoder) used in the High profile of the H.264/AVC video coding standard as a design example. The design is aimed to strike a balance between software modules and hardware modules based on design constraints. It is capable of decoding one bin per clock cycle at high clock frequencies while maintaining a slim hardware footprint. Compared to existing statistical decoders, this design is aimed for a fast and compact IP core, well verified with standard video test sequence, and ideal for a SoC implementation.